DK-DEV-5SGXEA7N【PDF 4/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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TOC-4

Stratix V Device Handbook Volume 1: Device Interfaces and Integration

Document Revision History.....................................................................................................................3-27

Clock Networks and PLLs in Stratix V Devices..................................................4-1

Clock Networks............................................................................................................................................4-1

Clock Resources in Stratix V Devices............................................................................................4-1

Types of Clock Networks................................................................................................................4-2

Clock Sources Per Quadrant..........................................................................................................4-7

Types of Clock Regions...................................................................................................................4-8

Clock Network Sources...................................................................................................................4-9

Clock Output Connections...........................................................................................................4-11

Clock Control Block......................................................................................................................4-11

Clock Power Down........................................................................................................................4-13

Clock Enable Signals......................................................................................................................4-14

Stratix V PLLs.............................................................................................................................................4-15

PLL Physical Counters in Stratix V Devices..............................................................................4-16

PLL Locations in Stratix V Devices.............................................................................................4-17

PLL Migration Guidelines ...........................................................................................................4-23

Fractional PLL Architecture.........................................................................................................4-24

PLL Cascading................................................................................................................................4-25

PLL External Clock I/O Pins........................................................................................................4-25

PLL Control Signals.......................................................................................................................4-26

Clock Feedback Modes..................................................................................................................4-27

Clock Multiplication and Division..............................................................................................4-34

Programmable Phase Shift............................................................................................................4-35

Programmable Duty Cycle...........................................................................................................4-35

Clock Switchover...........................................................................................................................4-35

PLL Reconfiguration and Dynamic Phase Shift........................................................................4-40

Document Revision History.....................................................................................................................4-40

I/O Features in Stratix V Devices........................................................................5-1

I/O Standards Support in Stratix V Devices.............................................................................................5-2

I/O Standards Support in Stratix V Devices.................................................................................5-2

I/O Standards Voltage Levels in Stratix V Devices.....................................................................5-3

MultiVolt I/O Interface in Stratix V Devices...............................................................................5-6

I/O Design Guidelines for Stratix V Devices...........................................................................................5-6

Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards.............................5-6

Guideline: Use the Same V CCPD for All I/O Banks in a Group.................................................5-7

Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing........................5-8

Altera Corporation

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